Verific — head and shoulders above the rest Product · SnapRTL

SnapRTL

An automated HDL editor. Analyze, modify, and export designs while preserving original code and formatting.

Get started: Run SnapRTL once to register your machine — you'll get a free 14-day trial of every feature. After the trial, you'll have a free-tier license; purchase individual features below to unlock advanced functionality.

Description

SnapRTL is a powerful productivity tool for Verilog and SystemVerilog that can make text-based design modification for DFT and other applications, while preserving the original formatting and comments of the original RTL design. Using a single Tcl command, users can add ports, connect signals, move instances, and export updated source files without disrupting the existing code structure. During the analysis phase, SnapRTL provides comprehensive feedback and error checking to ensure modifications are applied accurately. Users can specify the complete hierarchical path to precisely identify the location of ports or signals, enabling reliable, error-free connections. By automating repetitive RTL editing tasks and minimizing the risk of manual errors, SnapRTL significantly improves productivity, enhances design reliability, and reduces the time required to modify large and complex design files. You can read more about in the Documentation.

Product Configuration

SnapRTL is available as a free base product with essential functionality. To extend its capabilities, you can enable individual premium features based on your workflow. New users receive a 14-day free trial with access to all premium features, allowing you to evaluate the complete SnapRTL experience before making a purchase. After the trial ends, your license automatically reverts to the free tier, and you can subscribe to only the features you need. Each feature is billed monthly, can be enabled or disabled independently, and automatically renews until canceled.

SnapRTL Base
Includes the Verific HDL Analyzer and core text-based RTL editing. Analyze Verilog and SystemVerilog designs, add or remove ports, nets, instances, and connections, insert custom RTL, and write modified source files while preserving existing formatting and comments.
Free INCLUDED

Select features to purchase. Each is $25/month (or as priced below) and stays active for 30 days from purchase, auto-renewing monthly. Cancel anytime in your account.

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Note: SnapRTL uses automatic identity-based licensing. On first run, you'll register your machine via your browser and receive a 14-day trial with all features enabled. After trial, you'll have a free-tier license; any features you've purchased remain active.

Playground

Try SnapRTL instantly in your browser with the Playground. Explore the full feature set without installing any software, experiment with RTL modifications, and use the built-in AI assistant to generate Tcl scripts, answer questions, and accelerate your workflow. The Playground is intended for evaluation and learning and supports designs up to a limited size. For larger projects and unrestricted usage, download the desktop version of SnapRTL.

Downloads

PlatformVersionDownload
Linux x86_64 Jul26
macOS Jul26
Windows Coming soon

Installation

  1. Download your platform archive (current: Jul26).
  2. Extract the archive to a folder on your machine.
  3. First run — Identity registration:
    • Navigate to <installation_dir>/bin
    • Run snap-rtl (./snap-rtl)
    • Tool displays registration URL
  4. Browser registration:
    • Open URL in browser
    • Log in with Verific Store credentials
    • Website displays registration code
    • Copy code back to terminal
  5. License activation:
    • You will begin a 14-day trial with all features enabled.
    • After the trial, you'll have a free-tier license. Features you've purchased on this page remain active and renew monthly.

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