LintRTL – Verific Store

Get started: Run LintRTL once to register your machine — you'll get a free 14-day trial of every feature. After the trial, you'll have a free-tier license; purchase individual features below to unlock advanced functionality.

Description

LintRTL is a comprehensive static analysis tool for Verilog, SystemVerilog, and VHDL that helps designers identify coding, structural, and synthesizability issues early in the development cycle. By analyzing RTL source code without requiring simulation or synthesis, LintRTL detects potential design problems, enforces coding standards, and promotes consistent, high-quality RTL development. Its configurable rule set enables teams to tailor linting checks to their design guidelines, while built-in synthesizability analysis highlights common synthesis-related issues before implementation. By automating RTL quality checks, LintRTL improves code reliability, accelerates design reviews, and helps teams maintain robust and maintainable hardware designs across projects of any scale. You can read more about in the Documentation.

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Product Configuration

LintRTL includes a comprehensive set of core linting capabilities, with optional premium rule packs that extend static analysis for specialized verification tasks. Premium features include advanced synthesis analysis for detecting synthesis-related RTL issues and additional language-specific rule sets such as VHDL support. New users receive a 14-day free trial with access to all premium features, allowing them to evaluate the complete LintRTL rule set before purchasing. After the trial expires, the license reverts to the free tier, and users can subscribe only to the features they need.

LintRTL Base

Includes the Verific HDL Analyzer for Verilog, SystemVerilog, and VHDL designs. Analyze source files with syntax and semantic checks and build the internal design representation used by LintRTL features.

Free INCLUDED

Select features to purchase. Each is $25/month (or as priced below) and stays active for 30 days from purchase, auto-renewing monthly. Cancel anytime in your account.

Advance Lint Synthesis checks

$25.00/mo

Perform synthesizability validation identical to standard RTL synthesis tools, at a fraction of the runtime.

Lint VHDL Rules

$25.00/mo

Applies LintRTL's rule checks to VHDL designs, in addition to Verilog and SystemVerilog

Note: LintRTL uses automatic identity-based licensing. On first run, you'll register your machine via your browser and receive a 14-day trial with all features enabled. After trial, you'll have a free-tier license; any features you've purchased remain active.

Playground

Try LintRTL instantly in your browser with the Playground. Analyze Verilog, SystemVerilog, and VHDL designs using LintRTL's static analysis engine without installing any software. Explore coding rule violations, structural issues, and synthesizability checks, and use the built-in AI assistant to better understand reported diagnostics and improve code quality. The Playground is ideal for evaluation and learning, but it is limited to smaller designs. For large projects and unrestricted analysis, download the desktop version of LintRTL.

Playground

Downloads

Platform	Version	Download
Linux x86_64	Jul26	Sign in
macOS	Jul26	Sign in
Windows	–	Coming soon

Installation

Download your platform archive (current: Jul26).
Extract the archive to a folder on your machine.
First run — Identity registration:
- Navigate to <installation_dir>/bin
- Run lint-rtl (./lint-rtl)
- Tool displays registration URL
Browser registration:
- Open URL in browser
- Log in with Verific Store credentials
- Website displays registration code
- Copy code back to terminal
License activation:
- You will begin a 14-day trial with all features enabled.
- After the trial, you'll have a free-tier license. Features you've purchased on this page remain active and renew monthly.