Verific — head and shoulders above the rest Product · HierRTL

HierRTL

A Design Hierarchy Explorer. Ultrafast report of the structural hierarchy of Verilog, SystemVerilog, and VHDL RTL designs.

Get started: Run HierRTL once to register your machine — you'll get a free 14-day trial of every feature. After the trial, you'll have a free-tier license; purchase individual features below to unlock advanced functionality.

Description

HierRTL is a lightweight design-hierarchy exploration and reporting tool for Verilog, SystemVerilog, VHDL, and mixed-language designs. It analyzes the source-level parse tree to display modules, entities, instances, and generate constructs without requiring elaboration. Users can view the hierarchy as a readable tree, report a specific design root, recursively explore the full instance hierarchy, include source-file and line information, or export the results to a log file. HierRTL also provides hierarchical paths as a Tcl list, making it easy to automate design navigation and integrate hierarchy information into custom scripts and verification workflows.

Product Configuration

HierRTL includes core hierarchy-reporting capabilities for exploring Verilog, SystemVerilog, VHDL, and mixed-language designs. Users can report selected design roots, recursively inspect full hierarchies, display source-file and line information, save reports to a file, and retrieve instance paths for use in Tcl scripts. Additional premium capabilities may be introduced in future releases to support more advanced hierarchy analysis and design-navigation workflows. There are currently no purchasable features available for HierRTL—check back soon for updates.

HierRTL Base
Includes the Verific HDL Analyzer and HierRTL hierarchy exploration tools. Analyze Verilog, SystemVerilog, VHDL, and mixed-language designs, report source-level design hierarchies, recursively explore instances and generate constructs, and retrieve hierarchical paths for use in Tcl scripts.
Free INCLUDED
All HierRTL features are included in the base product for FREE.
Note: HierRTL uses automatic identity-based licensing. On first run, you'll register your machine via your browser and receive a 14-day trial with all features enabled. After trial, you'll have a free-tier license; any features you've purchased remain active.

Playground

Experience HierRTL directly in your browser with the Playground. Analyze Verilog, SystemVerilog, VHDL, or mixed-language source files and explore their structural hierarchy without installing any software. Generate readable hierarchy trees, inspect instances and generate blocks, explore complete hierarchical paths, and use Tcl commands to experiment with reporting options. The Playground is intended for evaluation and learning and supports designs up to a limited size. For larger projects and unrestricted usage, download the desktop version of HierRTL.

Downloads

PlatformVersionDownload
Linux x86_64 Jul26
macOS Jul26
Windows Coming soon

Installation

  1. Download your platform archive (current: Jul26).
  2. Extract the archive to a folder on your machine.
  3. First run — Identity registration:
    • Navigate to <installation_dir>/bin
    • Run hier-rtl (./hier-rtl)
    • Tool displays registration URL
  4. Browser registration:
    • Open URL in browser
    • Log in with Verific Store credentials
    • Website displays registration code
    • Copy code back to terminal
  5. License activation:
    • You will begin a 14-day trial with all features enabled.
    • After the trial, you'll have a free-tier license. Features you've purchased on this page remain active and renew monthly.

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